An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Abstract

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-/spl mu/m CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply.