Ferroelectric DRAM (FEDRAM) FET with metal/SrBi/sub 2/Ta/sub 2/O/sub 9//SiN/Si gate structure

Abstract

N-channel ferroelectric dynamic random access memory (FEDRAM) FETs with SrBi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O/sub 9//SiN/Si structure were fabricated and characterized. The estimated switching time (t/sub sw/) of the fabricated FET, measured at applied electric field of 376 kV/cm, was less than 50 ns, which could be significantly reduced upon scaling. Its remnant polarization (2P/sub r/) was measured to be about 1.5 μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is more than one order of magnitude higher than that required for FEDRAM operation. The stored information retains more than three orders of magnitude of on/off ratio up to three days at room temperature, with little fatigue after 10/sup 11/ switching cycles.