Concepedia

A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI

W.D. Dettloff, J.C. Eble, Lei Luo, Pravin Kumar, Fred Heaton, Teva Stone, Barry Daly

2010 · 46 citations · 3 references

Concepts

Sst TransmitterElectrical EngineeringEngineeringVlsi DesignClock RecoveryTiming AnalysisMixed-signal Integrated CircuitGround RegulationComputer EngineeringElectronic CircuitCmos SoiCommunication CircuitMicroelectronicsSignal ProcessingSignal IntegrityAnalog-to-digital ConverterWeighted Segments

Abstract

An SST transmitter is described with ground regulation, P-to-N shunting and partially weighted segments for fine granularity level/equalization. Clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV eye for a power efficiency of 4.32mW/(Gb/s). Measured total jitter is 209.6mUI or 28.3ps at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> BER. Target protocols include PCIe G1/2, XAUI, FC 1/2/4, CEI6 MR and SATA 1/2.

References

3

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

John W. Poulton, R. Palmer, Andrew M. Fuller et al. · IEEE Journal of Solid-State Circuits · 2007 · 239 citations

Low-power Electronics, Wireless Communications, Electrical Engineering +12

A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI

Christian Menolfi, Thomas Toifl, Peter Buchmann et al. · 2007 · 62 citations

Electrical Engineering, Engineering, Vlsi Design +12

A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS

Marcel Kossel, Christian Menolfi, Peter Buchmann et al. · 2008 · 14 citations

Low-power Electronics, Electrical Engineering, Engineering +13