Design methodology for deep submicron CMOS

Abstract

A design methodology for optimizing deep submicron CMOS devices is proposed, where gate oxide thickness T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> and supply voltage V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> are the main parameters. An operational region where all the constraints are satisfied, is represented in a simple 2D (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> -T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> ) plane. Parameter optimization for realizing high performance of given circuits can be achieved with excellent prospects. This method was utilized for 0.25µm CMOS design to demonstrate its usefulness. Optimum supply voltage and oxide thickness are expected to be 2V and 6nm, respectively. Sensitivity analysis showed that a surface channel is preferable to a buried channel.