A 60-GHz 0.13-$\mu{\hbox{m}}$ CMOS Divide-by-Three Frequency Divider

Abstract

This paper presents the design and analysis of a 60-GHz 0.13-mum CMOS divide-by-three frequency divider (FD). The regenerative injection-locked technique is proposed to achieve divide-by-three function at millimeter-wave frequency. The novel level shifter is used to increase the overdrive voltage of the input switch of the loop divider such that the divider locking range and input sensitivity can be enhanced. The CMOS divide-by-three FD including the testing pads occupies the silicon area of 0.99 mm × 0.69 mm. Operated at 1.3 V, the CMOS divider consumes 13 mW of power. The measured locking range is 1.8 GHz around the input frequency of 59 GHz, and the phase noise of the output signal at 1-MHz offset is -131.36 dBc/Hz.