2010 · 10 citations · 11 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureParallel ComputingSystem-on-chip DesignCachingCaching StrategiesData CompressionData ParallelismParallel ArchitecturesParallel Computer ArchitectureBufferingCache Hierarchy DesignCache PrefetchingData PrefetchingDecoder DesignHardware PipeliningPipeliningPrefetching
In this paper, we propose parallelization and optimization techniques of the H.264 decoder for the Cell BE processor. We exploit both frame-level parallelism and macroblock pipelining. The major bottleneck in achieving the real-time performance is the entropy decoding stage, CABAC. Our decoder eliminates this bottleneck by exploiting the frame-level parallelism available in the entropy decoding stage. A macroblock software cache and a prefetching technique for the cache are used to facilitate macroblock pipelining. In addition, an asynchronous macroblock buffering technique is used to eliminate the effect of load imbalance between pipeline stages. We evaluate the effectiveness of our approach by implementing a parallel H.264 decoder on an IBM Cell blade server. The evaluation results indicate that our parallel H.264 decoder (with CABAC entropy decoding) on a single Cell BE processor meets the real-time requirement of the full HD standard at level 4.0. Moreover, our decoder also satisfies the real-time requirement at level 4.1 when an additional Cell BE processor is used.
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Introduction to the Cell multiprocessor
J. Kahle, Michael Day, H. Peter Hofstee et al. · IBM Journal of Research and Development · 2005 · 941 citations
Synergistic Processing in Cell's Multicore Architecture
Michael Gschwind, H. Peter Hofstee, B. Flachs et al. · IEEE Micro · 2006 · 406 citations
Chip multiprocessing and the cell broadband engine
Michael Gschwind · 2006 · 131 citations