Cache Hierarchy Design

Cache Hierarchy Design is a foundational architectural methodology in multicore processor design that systematically organizes memory storage levels by defining the structure, placement, and interaction of caches to optimize data access latency, bandwidth utilization, and power efficiency across multiple cores.

511

Publications

31.2K

Citations

1.5K

Authors

313

Institutions

Publications per year

2017–2026

67

Authors

1.5K

  1. YX
    Yuan Xie

    Pennsylvania State University, United States

    10 publications · 871 citations

    10

    h-index

  2. MK
    Mahmut Kandemir

    Pennsylvania State University, United States

    9 publications · 454 citations

    9

    h-index

  3. RB
    Rajeev Balasubramonian

    University of Utah, United States

    8 publications · 689 citations

    8

    h-index

  4. JS
    Julio Sahuquillo

    Universitat Politècnica de València, Spain

    7 publications · 151 citations

    7

    h-index

  5. CK
    Changkyu Kim

    Intel (United States), United States

    7 publications · 903 citations

    7

    h-index

1–5 of 1.5K

Venues

  1. ACM SIGARCH Computer Architecture News

    26 publications · 1.4K citations

    19

    h-index

  2. IEEE Micro

    16 publications · 1.2K citations

    15

    h-index

  3. IEEE Transactions on Computers

    13 publications · 376 citations

    11

    h-index

  4. IBM Journal of Research and Development

    10 publications · 332 citations

    10

    h-index

  5. IEEE Journal of Solid-State Circuits

    8 publications · 428 citations

    8

    h-index

1–5