EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignSystem-on-chip DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Logic DesignIntegrated Circuit DesignLayout OptimizationPhysical DesignArea OptimizationArea-efficient DesignArea-efficient Logic Block DesignDigital Circuit OptimizationLayout TechniquesLogic Block DesignLogic Gate ImplementationLogic Optimization
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.
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Logic Design and Switching Theory
D. Everett · Electronics and Power · 1980 · 195 citations
One-dimensional logic gate assignment and interval graphs
Tomi Ohtsuki, H. Mori, E.S. Kuh et al. · IEEE Transactions on Circuits and Systems · 1979 · 107 citations
Engineering, Computer Engineering, Electrical Engineering +15
SHARPS: A Hierarchical Layout System for VLSI
Toru Chiba, Noboru Okuda, Takashi Kambe et al. · Design Automation Conference · 1981 · 31 citations