Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor

Abstract

It is shown that systolic array design techniques commonly used by VLSI designers can be used to realize neural nets on parallel single-instruction-multiple-data (SIMD) machines. The MasPar MP-1 is well suited for implementation of 2D systolic arrays because of its X-network communications. Implementation of neural networks can be further optimized by taking advantage of other architectural features: indirect addressing, register-based CPU, and large addressable local memories. An application to speech recognition is discussed