International Journal of Future Computer and Communication · 2013 · 36 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysLow-power DesignClock GatingDynamic Power ReductionField-programmable Gate Array ArchitectureFpga ArchitectureLow-power Fpga DesignPower ManagementArithmetic Logic Unit ArchitectureArithmetic Logic Unit DesignClock Gating In Field-programmable Gate ArraysDynamic Power DissipationLatch-based Clock GatingLeakage PowerLow-power Logic DesignLow-power Processor Design
This paper deals with the design and implementation of a Clock Gating Aware Low Power Arithmetic and Logic Unit that has been developed as part of low power processor design in the platform Xilinx ISE 14.2 and synthesized on 90nm Spartan-3 FPGA. Clock power contributes 45-60 percent of total dynamic power. Hence, clock power reduction is necessary in low power design. In this paper, we analyze theoretical 93.75% clock power reduction in ALU using clock gating techniques. On simulator, we achieved 88.23% clock power reduction using latch based clock gating and 70.58% clock power reduction using latch free clock gating. Index Terms—Clock gate, ALU, FPGA, LUT, clock power, register transfer level, dynamic power, leakage power
5
Clock gating and clock enable for FPGA power reduction
Juan Pablo Oliver, J. J. Curto, Diego Bouvier et al. · 2012 · 39 citations
Engineering, Computer Engineering, Electrical Engineering +17
Rapid Prototyping of a Self-Timed ALU with FPGAs
Susana Ortega Cisneros, Juan José Raygoza Panduro, Juan Suardíaz Muro et al. · 2006 · 25 citations