Latch-based Clock Gating

Latch-Based Clock Gating is a clock gating technique that employs a level-sensitive latch to control the propagation of the clock signal to downstream circuitry, distinguishing itself from flip-flop-based or pulse-triggered methods by enabling transparent hold conditions during active phases for reduced timing overhead in low-power digital designs.

3

Publications

94

Citations

15

Authors

4

Institutions

Publications per year

2017–2026

2

Authors

15

  1. SZ
    Shichang Zou

    Shanghai Institute of Microsystem and Information Technology, China

    2 publications · 58 citations

    2

    h-index

  2. JJ
    Jianwei Jiang

    University of Chinese Academy of Sciences, China

    2 publications · 58 citations

    2

    h-index

  3. WZ
    Wenyi Zhu

    University of Chinese Academy of Sciences, China

    1 publications · 34 citations

    1

    h-index

  4. HZ
    Haineng Zhang

    Shanghai Institute of Microsystem and Information Technology, China

    1 publications · 24 citations

    1

    h-index

  5. MP
    Manisha Pattanaik

    Atal Bihari Vajpayee Indian Institute of Information Technology and Management, India

    1 publications · 36 citations

    1

    h-index

1–5 of 15

Venues

  1. International Journal of Future Computer and Communication

    IJFCC · 1 publications · 36 citations

    1

    h-index

  2. 1

    h-index

  3. Electronics Letters

    1 publications · 34 citations

    1

    h-index

1–3