Latch-based Clock Gating
Latch-Based Clock Gating is a clock gating technique that employs a level-sensitive latch to control the propagation of the clock signal to downstream circuitry, distinguishing itself from flip-flop-based or pulse-triggered methods by enabling transparent hold conditions during active phases for reduced timing overhead in low-power digital designs.
3
Publications
94
Citations
15
Authors
4
Institutions
Publications per year
2017–2026
2
Parents
3
Low‐cost single event double‐upset tolerant latch design
Jianwei Jiang, Yiran Xu, Jiangchuan Ren et al. · Electronics Letters · 2018 · 34 citations
Engineering, Computer Engineering, Electrical Engineering +15
1–3 of 3
15
Shanghai Institute of Microsystem and Information Technology, China
2 publications · 58 citations
2
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2
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1
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Shanghai Institute of Microsystem and Information Technology, China
1 publications · 24 citations
1
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Atal Bihari Vajpayee Indian Institute of Information Technology and Management, India
1 publications · 36 citations
1
h-index
1–5 of 15
4
Shanghai Institute of Microsystem and Information Technology
Shanghai, China
2 h-index
13 publications
372 citations

Chinese Academy of Sciences
Beijing, China
2 h-index
13 publications
372 citations
University of Chinese Academy of Sciences
Beijing, China
1 h-index
6 publications
204 citations
Taiwan Semiconductor Manufacturing Company (China)
Shanghai, China
1 h-index
8 publications
272 citations
1–4 of 4
IJFCC · 1 publications · 36 citations
1
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1 publications · 24 citations
1
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1 publications · 34 citations
1
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1–3