Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory

Abstract

Optimal process integration for array devices of bit-cost scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors. With these technologies and newly devised 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell array, BiCS flash becomes a promising candidate for future ultra-high density memory.