IBM Journal of Research and Development · 1990 · 42 citations · 9 references
ComputingComputer ScienceInstructionCompilersComputer ArchitectureSchedulingCompiler ConstructionControl-flow AnalysisData-flow AnalysisInstruction SchedulingInstruction-level ParallelismPipeline ParallelismBasic Block SchedulingData Dependency ManagementData Dependency MappingInstruction Scheduling AlgorithmsMicroarchitectural OptimizationPipeline AnalysisPipeline SchedulingPipelining
Instruction scheduling consists of the rearrangement or transformation of program statements, usually at the intermediate language or assembly code level, in order to reduce possible run-time delays between instructions. Such transformations must preserve data dependency and are subject to other constraints. Highly optimizing compilers employing instruction-scheduling techniques have proven to be effective in improving the performance of pipeline processors. Considerable attention has been given to scheduling code within the scope of basic blocks, i.e., straight-line sections of code. In this paper we present techniques for scheduling beyond basic blocks. This allows a further reduction in run-time delays such as those due, e.g., to branches and loops, enabling the exploiting of pipeline architectures which would not otherwise be possible.
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Register allocation & spilling via graph coloring
Gregory J. Chaitin · ACM SIGPLAN Notices · 1982 · 767 citations · Full text
Register allocation via coloring
Gregory J. Chaitin, Marc Auslander, Ashok K. Chandra et al. · Computer Languages · 1981 · 731 citations
Register allocation & spilling via graph coloring
Gregory J. Chaitin · 1982 · 668 citations
Code scheduling and register allocation in large basic blocks
James Goodman, Wei‐Chung Hsu · 2014 · 178 citations