IEEE Journal of Solid-State Circuits · 1989 · 10 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignClock Distribution NetworksClock ManagementCmos Circuit DesignDesign For TestabilityIntegrated Circuit DesignTiming AnalysisClock DesignClock Network ArchitectureClock Skew MinimizationHigh-speed OperationSkew DeviationSkew EffectsSkew FieldsSkew Mitigation
Implementation of the TX1 VLSI microprocessor is described. Particular emphasis is placed on the design method, which meets the requirements of short design time with reasonable chip size. A one-phase clock system, which is a better solution for high-speed operation but requires careful design for evading the skew problem, is discussed. Design for testability is embedded in the chip. The TX1 is fabricated with a 1.0 mu m two-layer metal CMOS process. The chip contains 450 K transistors in a 10.89*10.27 mm/sup 2/ die.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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The TX1 32-bit microprocessor: performance analysis, and debugging support
M. Miyata, Hidechika Kishigami, K. Okamoto et al. · IEEE Micro · 1988 · 14 citations