An untrimmed D/A converter with 14-bit resolution

K. Maio, M. Hotta, N. Yokozawa, M. Nagata, Kenji KANEKO, Tomio Iwasaki

IEEE Journal of Solid-State Circuits · 1981 · 24 citations · 6 references

Concepts

Abstract

Describes a monolithic 14-bit DAC which uses a new compensation technique for the DAC linearity, the `self-compensation technique', originated through a new concept. Since this technique automatically compensates for linearity error in the DAC by referring to a ramp function with about 17-bit linearity, a high precision DAC can be produced in monolithic form without the trimming of analog components. An experimental 14-bit DAC chip has been fabricated using analog compatible IIL technology and two-level metalization. A linearity error of less that /spl plusmn/1/2 LSB and a settling time of 1-2 /spl mu/s has been achieved.

References

6