2007 · 22 citations · 4 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsClock Distribution NetworksClock ManagementClock SynchronizationJitter AnalysisLow-power Digital Circuit DesignTiming AnalysisClock DistributionClock GenerationClock Generation CircuitsClock Management UnitsCore Area DesignationJitterPower Consumption
A 2-to-5GHz multi-phase multi-period-locked DLL is fabricated in a 90nm CMOS technology. At 5GHz, the measured rms jitter is 0.874ps and the peak-to-peak jitter is 7.56ps. The multi-phase DLL is used for a 40GHz clock generator. The core area is 0.374times0.326mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 45mW at 1V.
4
A CMOS 50% duty cycle repeater using complementary phase blending
Kazuyuki Nakamura, M. Fukaishi, Y. Hirota et al. · 2002 · 51 citations
Engineering, Computer Engineering, Electrical Engineering +14