IEEE Journal of Solid-State Circuits · 2006 · 65 citations · 7 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignLow-noise Circuit DesignMixed-signal Integrated Circuit DesignNoise In Analog CircuitsRadio-frequency Integrated CircuitsUltra-wideband CommunicationBandwidthDelay-locked LoopsDiscrete-time ModelsFrequency SynthesisFrequency SynthesizersPhase NoisePhase Noise AnalysisSettling Time
A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-/spl mu/m CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.
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