Optimization of combinational logic circuits based on compatible gates

Abstract

Abstract- Thts paper prmenta a set of new teelmiques for the nptimtzattmr of multiple-level combtnattorud Boolean networks. Such teehntquea are breed on a temporary tmnsfonnatlon of the networ& tnto an internally unste one. We descrtbe tirat a teebnique baaed upon the seleetion of appropriate multiple-output subnetwo~s (consisting of s~c.slled comprztible gates) whose local functions can be opthntzed sttmdtaneoualy. We then generalize the method to larger subsets of tmate gates. Beeauae shntdtaneoua opttmizatton of local functions ean take place, our methods are more powerful and general than Boolean optimization methods using don t cares, where only single-gate opti. ndzatton am be performed. In addttton, our methods rvpmaent a more efficient alternative to Boolean rvlations-b=d opttndzation procedures beeauae the problem can be mndeled by a mate covertng problem tnstead of the more difficult binate eoverhtg problem. The method ts implemented in program achilks and compares favorably to ~S. 1