New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

Abstract

A new latch architecture based on a switchable hysteresis mechanism to improve the SEU hardness in hold mode and limit the delay penalty during write operation is proposed. This latch relies on the Schmitt trigger inverter schematic and has been named the Robust Schmitt Trigger (RST) latch. RST latch has been implemented in a 65 nm radiation test vehicle and upset rates have been measured during proton irradiations. Our design solution enhanced the SEU cross-section and divides by 2 the system level power consumption penalty compared to a DICE based design. The RST latch is an alternative between the DICE latch and the reference latch for soft radiative environments.