A dual grain hit-miss detector for large die-stacked DRAM caches

Abstract

Abstract—Die-Stacked DRAM caches offer the promise of improved performance and reduced energy by capturing a larger fraction of an application’s working set than on-die SRAM caches. However, given that their latency is only 50 % lower than that of main memory, DRAM caches considerably increase latency for misses. They also incur a significant energy overhead for remote lookups in snoop-based multi-socket systems. Ideally, it would be possible to detect in advance that a request will miss in the DRAM cache and thus selectively bypass it. This work proposes a dual grain filter which successfully predicts whether an access is a hit or a miss in most cases. Experimental results with commercial and scientific workloads show that a 158KB dual-grain filter can correctly predict data block residency for 85 % of all accesses to a 256MB DRAM cache. As a result, offdie latency with our filter is nearly identical to that possible with an impractical, perfect filter. I.