A High-Linearity $X$-Band Four-Element Phased-Array Receiver: CMOS Chip and Packaging

Abstract

This paper presents the design and chip-on-board packaging of a high-linearity four-element phased-array receiver for 9-10-GHz applications. The phased-array is built using 0.13-μm CMOS with a single-ended design, and it results in a measured gain of 10.1 dB, an input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of - 12.5dBm, an input IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -4 dBm, and a noise figure of 3.4 dB at 9.5 GHz. An rms gain error of <;0.4 dB and phase error of <;8° are obtained at 9-10 GHz using an integrated variable gain amplifier and an 11° phase trim bit. The chip occupies an area of 2.5 × 2.9 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a power consumption of 36 mW per channel from a 1.8-V supply (144-mW total). The phased array is packaged using chip-on-board techniques and the channel-to-channel coupling is determined either by the chip-to-ground inductance or by coupling between the input bond-wires. Measurements and simulations on channel 1 show that, with well isolated input bond-wires, one can obtain <; -31-dB coupling between the channels, and an rms amplitude and phase error of ~0.2 dB and ~1°, respectively, at 9.5 GHz, when the phase of channels 2-4 are changed. To our knowledge, this is the first in-depth study of coupling in a phased-array chip with packaging considerations.