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CMOS Low-Noise Amplifier Design Optimization Techniques

596

Citations

28

References

2004

Year

TLDR

The paper reviews four CMOS cascode LNA design techniques—classical noise matching, simultaneous noise and input matching (SNIM), power‑constrained noise optimization, and power‑constrained simultaneous noise and input matching (PCSNIM)—and analyzes their noise performance. It aims to clarify the design principles, limitations, and advantages of these techniques using derived noise‑parameter equations to give designers a comprehensive perspective. The authors introduce concise noise‑parameter expressions for SNIM and PCSNIM and demonstrate the PCSNIM principle by implementing a low‑power folded‑cascode LNA in 0.25‑µm CMOS for 900‑MHz Zigbee. Measurements show a 1.35‑dB noise figure, 12‑dB gain, –4 dBm third‑order intermodulation, and 1.6 mA supply current (0.7 mA for the input NMOS), confirming close agreement with theory.

Abstract

This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.

References

YearCitations

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