IEEE Transactions on Computers · 1988 · 23 citations · 6 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingFault-tolerant SystemsError DetectionFault DetectionFault ManagementHardware Fault ToleranceReliable System DesignSelf-checking CircuitsError Detection CircuitsFault Tolerance In Digital CircuitsFault-tolerant ArchitectureFault-tolerant Logic DesignSelf-checking DesignSelf-checking LogicTriple Modular Redundancy
A totally self-checking triple modular redundancy (TSC-TMR) system consists of a conventional TMR system monitored by a TSC circuit with two outputs indicating information errors and internal faults. The internal fault indication is independent of the output information errors and indicates masked errors of modular units or faults in the monitoring circuit itself. The information error indication depends mainly on the output information errors and it can be used as a stop signal preventing the propagation of erroneous outputs. This scheme of fault-tolerant systems is very simple and reliable compared to the known TMR systems with self-checking capabilities and achieves a high degree of availability and maintainability. The TSC error checking circuit has been designed by applying a new algebraic technique with two basic operator blocks performing the AND and XOR operations on error indication variables.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Design of dynamically checked computers.
William C. Carter, Peter R. Schneider · IFIP Congress · 1968 · 301 citations
Optimum test patterns for parity networks
D. C. Bossen, D. L. Ostapko, A. M. Patel · 1970 · 43 citations