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Optimum test patterns for parity networks
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Circuit ComplexityEngineeringError Control TechniqueVerificationComputer-aided VerificationNetwork AnalysisEducationSoftware AnalysisFormal VerificationHardware SecurityOptimum Test PatternsSystems EngineeringDiscrete MathematicsCombinatorial OptimizationParity TreeExclusive-or GatesComputer EngineeringComputer ScienceLogic DesignError Correction CodeNetwork AlgorithmTree StructureProgram AnalysisSoftware TestingFormal MethodsCombinatorial Testing WorkflowProperty TestingFault Injection
The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.