DP‐FPGA: An FPGA Architecture Optimized for Datapaths

Abstract

This paper presents a new Field‐Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask‐Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four‐bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four‐bit slices, reducing the total number of storage cells required. This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four‐bit carry skip circuit, a four‐bit register with enable and direct input capabilities, and four three‐state buffers. Further estimates of implementation area predict that the area of a design′s datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.