Journal of Physics Conference Series · 2014 · 28 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsField-programmable Gate ArraysAccelerator ArchitectureAccelerator IntegrationConfigurable Logic BlocksField-programmable Gate Array ArchitectureInterconnect ArchitectureNetwork-on-chip DesignEvent BusField-programmable System-on-chipFront-end ArchitectureFront-end DesignNetwork-on-chip ArchitecturesOn-board Data HandlingOn-chip InterconnectsOn-chip Networks
The architecture of the data acquisition system foreseen for the LHCb upgrade, to be installed by 2018, is devised to readout events trigger-less, synchronously with the LHC bunch crossing rate at 40 MHz. Within this approach the readout boards act as a bridge between the front-end electronics and the High Level Trigger (HLT) computing farm. The readout board baseline ATCA-based design requires dedicated crates and foresees the implementation of a local area network protocol directly in the readout board FPGAs. The alternative solution proposed here consists in building the readout boards as PCIe peripherals of the event-builder servers. The main architectural advantage is that protocol and link-technology of the event-builder can be left open until very late, to profit from the most cost-effective industry technology available at the time of the LHC LS2.
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S. Baron, R. Ballabriga, S. Bonacini et al. · CERN Document Server (European Organization for Nuclear Research) · 2009 · 121 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16