2013 · 44 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignChip PackagingCmos Circuit DesignIii-v SemiconductorsIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit Fabrication3D Integrated CircuitsCmos Logic CircuitsDigital Logic CircuitsInterlayer Dielectric IntegrationMonolithic ArchitectureStatic Noise MarginThree-dimensional Integrated Circuit LayoutThree-dimensional Integration
For the first time, a sequentially processed sub-50nm monolithic 3D IC with integrated logic/NVM circuits and SRAM is demonstrated using multiple layers of ultrathin-body (UTB) MOSFET-based circuits interconnected through 300nm-thick interlayer dielectric (ILD). High-performance sub-50nm UTB MOSFETs using deposited ultra-flat and ultra-thin (20nm) epi-like Si enable across-layer and in-layer high-speed 3ps logic circuits and 1-T 500ns plasma-MONOS NVMs as well as 6T SRAMs with static noise margin (SNM) of 280 mV and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.
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Advances, challenges and opportunities in 3D CMOS sequential integration
P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text
Advances in 3D CMOS sequential integration
P. Batude, M. Vinet, A. Pouydebasque et al. · 2009 · 115 citations
Engineering, Computer Engineering, Electrical Engineering +15
Monolithic 3D Integrated Circuits
S.S. Wong, Abbas El-Gamal, Peter Griffin et al. · 2007 · 105 citations
Engineering, Computer Engineering, Electrical Engineering +17
High density 3D integration using CMOS foundry technologies for 28 nm node and beyond
Jason Lin, W.C. Chiou, K.F. Yang et al. · 2010 · 70 citations
Investigation on TSV impact on 65nm CMOS devices and circuits
H. Chaabouni, Maxime Rousseau, Philip R. LeDuc et al. · 2010 · 54 citations
Engineering, Computer Engineering, Electrical Engineering +17