SEU concept to reality (allocation, prediction, mitigation)

Abstract

For a number of years products are being impacted by transient faults that cause the systems to fail and returned to suppliers as returned material authorization (RMA). After further analysis, they deemed to be good and no problem found and ultimately sent back out to potential customers and replacements. These returns are most likely being caused by Single Event Upsets. The phenomenon of Single Event Upset (SEU) is a well known and documented and affects electronic circuitry. SEUs are caused by either atmospheric neutrons or alpha particles emitted by trace impurities in the silicon processing and packaging materials. SEUs could cause single or multiple bit errors in the components such as ASCIs, FPGAs, processors and memories. All of these components are susceptible to SEU, but in the traditional reliability analysis of products, these failures are not included. Reliability engineers calculate the failure rate for components based on hard failures and are totally discounting the Soft Error failures. In addition, when reliability engineers are performing availability modeling and failure allocation, SEUs are not included in their analysis. Therefore, the accuracy of their analysis could be questionable. The goal of this paper is to discuss the allocation, Prediction and mitigation of SEU in the design. It is hard to believe a reliability analysis of a component or a board is completed without any consideration to SEU. This paper will discuss the following: 1) Concept of SEU and what is Single Event Upset (SEU) and sources of SEU 2) Example of field events 3) SEU failure rate allocation 4) SEU prediction 5) SEU Mitigation 6) SEU best practices The methodology discussed in this paper can be applied to any integrated system that is required to meet a particular high availability target.