GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

Abstract

Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL. Suppression of GIDL by as much as two orders of magnitude can be realized by formation of steep underlapped junctions for both doped- and undoped-channel devices. The prospect of low leakage levels in doped-channel high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> FinFETs makes them suitable for memory cell applications.