Coreless substrate technology investigation for ultra-thin CPU BGA packaging

Abstract

Coreless packaging is an attractive option to meet the low z-height requirements typically demanded in low-profile mobile devices. In order to deliver high quality, fully functional assembled coreless packages several aspects of this technology need to be studied to understand the benefits and the drawbacks. Towards realizing this goal, a prototype coreless BGA package for an existing product was designed, fabricated, and characterized for power delivery and IO signal integrity. A comparative study of performance was performed on a 45nm CPU in a coreless BGA package, and compared to the same 45nm CPU in the standard cored BGA. This paper reviews the design strategies implemented and characterization data collected to achieve matched electrical performance with the existing cored package. The paper first makes comparisons between cored and coreless designs and then presents the detailed physical design concepts. Next the paper focuses on electrical performance analysis including both IO performance and power delivery analysis, and then reviews the validation data collected. The results of this study show that the IO performance is comparable between the cored and coreless packages for both microstrip and the stripline routing for both DDR3 and PCI Express Gen 2. Additionally, the power delivery study shows that the expected benefit from the removal of PTH's is compromised in this prototype design due to the removal of die side capacitors and the reduction in the total number of land side capacitors. This made the coreless DC loadline virtually unchanged when compared to the cored package.