High performance full adder cell: A comparative analysis

Abstract

Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. The present study proposes an energy efficient full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed. Result shows 45% improvement in threshold loss problem, 40% improvement in power-delay product over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies.