Structured logic design of integrated circuits using the storage/logic array (SLA)

Abstract

The Storage/Logic Array (SLA), a form of structured logic derived from PLA's, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLA's are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLA's) are made. Segmenting SLA's with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLA's in I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L, NMOS, and CMOS are described and compared, I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSI. Programming techniques and examples are given.