IEEE Journal of Solid-State Circuits · 2014 · 42 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignBackground CalibrationBicmos TechnologyCmos Analog Circuit DesignPower ConsumptionSige Bicmos Design
This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 µm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{-9}$</tex></formula> , and has a power consumption of 1.15 W for the core ADC.
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Time interleaved converter arrays
W.C. Black, D.A. Hodges · IEEE Journal of Solid-State Circuits · 1980 · 822 citations
Engineering, Computer Engineering, Electrical Engineering +16