Selective Electroless Ni‐Cu(P) Deposition for Via Hole Filling and Conductor Pattern Cladding in VLSI Multilevel Interconnection Structures

Abstract

The selective lectroless Ni-Cu(P) deposition process has been investigated for via hole filling and conductor pattern cladding in VLSI multilevel interconnection structures. Cu was added to A1-Si in order to deposit Ni-Cu(P) on A1-Si-Cu lines without any activation step and obtain a good selectivity. It was observed that a 0.2 ~m Ni-Cu(P) overcoat on a 0.5 ~tm A1-Si-Cu line increases corrosion resistance, suppresses hillock formation, and decreases the resistance of intercon-nection. The Ni-Cu(P) was deposited into via holes on Ni-Cu(P) overcoats of A1-Si-Cu lines without any activation. Via holes in a 1.5 ~m polyimide layer were filled by Ni-Cu(P) to the top surface to give completely planarization of intercon-nections. Good contact resistance has also been obtained without any nealing by measuring the via chain resistance. For comparison, selective lectroless Ni(P) deposition on A1-Si with Pd activation was also investigated. Undesired Ni(P) deposition on a dielectric surface (SiO2) between A1-Si lines was obtained after electroless Ni(P) deposition with Pd activa-tion of A1-Si lines. The electric potential distribution between aluminum lines on a dielectric layer (SIO2) was estimated using Poisson's equation to explain the poor selectivity due to surface activation of dielectric after the treatment i a Pd solution. With the continued ecrease in device dimensions and the increase in scale of integration, modem very large