IEEE Journal of Solid-State Circuits · 2004 · 28 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSensorsCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyImage SensorsLow-noise Circuit DesignNoise In Semiconductor DevicesPhotodetectorsCmos Image SensorsComplementary Metal-oxide-semiconductor Image SensorsCorrelated Double SamplingDouble SamplingImage Sensor DesignImage Sensor TechnologyPixel ArchitectureSaturation
New CMOS image sensors that can realize high quality dark scene images with pixels smaller than conventional pixel types are described. The new technologies used to develop them are floating diffusion (FD) driving pixel with a buried photodiode with three or less transistors, and low-voltage driving technologies with a new photodiode structure and FD-boost method. Through the use of the 0.25-/spl mu/m technology, prototype chips consisting of 3.45-/spl mu/m size pixels were manufactured. Prototype chips consisting of 3.1-/spl mu/m size pixels which share FD between two neighboring pixels (2-pixel-sharing) were also manufactured. The complete transfer operation, that is to say, zero lag and zero pixel kTC noise was achieved at a supply voltage of 2.5 V with manufacturing stability. Realized saturation voltages were 510 and 360 mV for 3.45-/spl mu/m and 3.1-/spl mu/m size pixel chips, respectively. In addition, a combined double-correlated double sampling (CDS) architecture which can flexibly process two sets of signals in combination were employed. Due to its small pixel size, high image quality, and output flexibility, this framework has potential for replacing charge-coupled device (CCD) image sensors with CMOS image sensors in volume markets of digital still cameras and camcorders.
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No image lag photodiode structure in the interline CCD image sensor
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CMOS image sensors: electronic camera on a chip
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