Architecting advanced technologies for 14nm and beyond with 3D FinFET transistors for the future SoC applications

Abstract

Industry's extensive knowledge of fabricating bulk CMOS planar transistors has made them the device of choice for the cost sensitive foundry semiconductor sector. On advanced nodes the scaling benefits for SoCs will be based on a set of Key Performance Indicators (KPIs) (Fig.1) quantified by measurable Figures of Merit (FOMs). These KPIs cover a range of requirements from system level performance, power, and die area scaling to manufacturing cost, production risk, reliability limitations, designabilty and technology extension for a broad domain of SoCs. Critical performance FOMs include Fmax, compute density performance at constant power density (MHz/mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and performance vs. power for a given cost (PPC) (MHz/mW/$). The idea is to integrate the transistor and physical scaling benefits to offer a cost sensitive technology platform that provides value for the SoC applications and effectively for the end users. Fig. 1 illustrates the complexity of achieving this task to minimize the risk and TTV/TTM while addressing the difficult technical barriers. Device and circuit co-optimization enhances the SoC values measured by PPC, PPA, and Fmax.