Reliability limits for the gate insulator in CMOS technology

Abstract

Aggressive scaling of the thickness of the gate insulator in CMOS transistors has caused the quality and reliability of ultrathin dielectrics to assume greater importance. This paper reviews the physics and statistics of dielectric wearout and breakdown in ultrathin SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -based gate dielectrics. Estimating reliability requires an extrapolation from the measeurment conditions (e.g., higher voltage) to normal operation conditions. To reduce the error in this extrapolation, long-term (>1 year) stress experiments have been used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. Measured over a sufficiently wide range of stress conditions, the time to breakdown (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> ) does not obey any simple “law” such as exponential dependence on electric field or voltage, as has been commonly assumed in reliability extrapolations. Thus, the interpretation of T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> data remains somewhat controver sial. Present research is aimed at better understanding the nature of the electrical conduction through a breakdown spot, and the effect of the oxide breakdown on device and circuit performance. In some cases an oxide breakdown may not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.