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On static compaction of test sequences for synchronous sequential circuits
119
Citations
6
References
1996
Year
Unknown Venue
EngineeringMem TestingVerificationClock SynchronizationFormal VerificationHardware SecurityTest SequencesDiscrete MathematicsAsynchronous CircuitsHardware-in-the-loop SimulationTesting TechniqueSynchronous DesignComputer EngineeringBuilt-in Self-testComputer ScienceDesign For TestingSoftware TestingAlert PreferencesFormal MethodsCombinatorial Testing WorkflowStatic CompactionFault Injection
Article Free Access Share on On static compaction of test sequences for synchronous sequential circuits Authors: Irith Pomeranz Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA Electrical and Computer Engineering Department, University of Iowa, Iowa City, IAView Profile , Sudhakar M. Reddy Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA Electrical and Computer Engineering Department, University of Iowa, Iowa City, IAView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 215–220https://doi.org/10.1145/240518.240558Published:01 June 1996Publication History 114citation239DownloadsMetricsTotal Citations114Total Downloads239Last 12 Months7Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
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