A 2K-gate GaAs gate array with a WN gate self-alignment FET process

Abstract

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.