Y. Kitaura - Concepedia

Author

Y. Kitaura

Toshiba (Japan)

Also Known As

Tetsuya Ito, Y. Kitaura, Yoshiaki KITAURA, Yoshiaki Kitaura, Yoshiaki Kitaura Yoshiaki Kitaura

Publications

279

Citations

H-Index

Concepts

All Affiliations

Toshiba (Japan)

About

Y. Kitaura is an author at Toshiba (Japan) specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	135
2	Electrical Engineering	9	9	135
3	Applied Physics	4	4	45
4	Computer Engineering	2	2	38
5	Physics	1	1	12

Y. Kitaura

Publications

135

Citations

H-Index

Page 1

	Year	Citations
A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system Kenji Ishida, H. Wakimoto, K. Yoshihara, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsUltrahigh-speed 8-B Multiplexer	1991	27
A novel resonant-type GaAs SPDT switch IC with low distortion characteristics for 1.9 GHz personal handy-phone system K. Kawakyu, Yoshiko Ikeda, M. Nagaoka, Low-power ElectronicsElectrical EngineeringSecond Order DistortionEngineeringRf Semiconductor	2002	24
High-efficiency monolithic GaAs power MESFET amplifier operating with a single low voltage supply for 1.9-GHz digital mobile communication applications M. Nagaoka, T. Inoue, K. Kawakyu, Low-power ElectronicsElectrical EngineeringEngineeringRf SemiconductorPower Amplifier	2002	15
Refractory WN<sub>x</sub>/W Self-Aligned Gate GaAs Power Metal-Semiconductor Field-Effect Transistor for 1.9-GHz Digital Mobile Communication System Operating with a Single Low-Voltage Supply Masami Nagaoka, Kenji Ishida, T. Matsunaga, Japanese Journal of Applied Physics Low-power ElectronicsElectrical EngineeringEngineeringRf SemiconductorHigh-frequency Device	1994	13
A 2K-gate GaAs gate array with a WN gate self-alignment FET process N. Toyida, Naotaka Uchitomi, Y. Kitaura, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringChip SizeEngineeringVlsi Design	1985	12
A self-aligned gate GaAs MESFET with p-pocket layers for high-efficiency linear power amplifiers K. Nishihori, Y. Kitaura, M. Hirose, IEEE Transactions on Electron Devices Low-power ElectronicsElectrical EngineeringEngineeringRf SemiconductorNanoelectronics	1998	12
A 42ps 2K-gate GaAs gate array Nagaoki Toyoda, Naotaka Uchitomi, Y. Kitaura, EngineeringVlsi DesignIntegration LevelComputer ArchitectureHardware Architecture	1985	11
A 2-V operation RF front-end GaAs MMIC for PHS hand-set T. Seshita, K. Kawakyu, H. Wakimoto, Rf SubsystemElectrical EngineeringPhs Hand-setEngineeringRadio Frequency	2002	11
Refractory WN Gate Self-Aligned GaAs MESFET Technology and Its Application to Gate Array IC's Naotaka Uchitomi, Y. Kitaura, Takamaro Mizoguchi, Electrical EngineeringSemiconductor DeviceEngineeringNanoelectronicsElectronic Engineering	1984	10

Page 1