2013 · 12 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignClock ManagementCmos Circuit DesignDigital Integrated Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationTiming AnalysisDelay-locked LoopsHigh-speed Cmos Design
A fast-locking digital delay-locked loop (DLL) is presented in this paper. By adopting a novel high resolution Time-to-Digital Converter (TDC), the time for generating fine-tuned codes is reduced to two clock cycles. Thus the total locking time is greatly reduced to 8 input reference clock cycles and remarkably shortened by 80% to 94.6% compared to previous closed-loop architectures. The proposed DLL has been fabricated in a 0.13μm CMOS technology and operates from 80MHz to 450MHz. The measured RMS and peak-to-peak jitters are 2.3ps and 10ps respectively.
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