An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This brief proposes a novel circuit architecture of an 11-bit reversible successive approximation register (RSAR)-controlled all-digital delay-locked loop (DLL), which could achieve adaptive bandwidth in a wide operation range by utilizing the modified binary search algorithm of the RSAR scheme. Moreover, it is fast locking because it finds the suitable delay range first and the successive approximation register process next. The proposed RSAR DLL is fabricated into a <formula formulatype="inline"><tex Notation="TeX">$0.2 \times 0.1\ \hbox{mm}^{2}$</tex></formula> silicon with SMIC 0.13-<formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> 1P6M complimentary metal–oxide–semiconductor technology. Test shows that the chip could work in a wide frequency range from 30 MHz to 1 GHz, with less than 42 cycles lock-in time, 10-ps delay resolution, and 1.5 mW at 30-MHz power dissipation. </para>