Design Automation Conference · 1981 · 14 citations · 5 references
ArchitectureDesignComputer-aided DesignDesign ComputationGeometric ModelingDesign SynthesisVery-large-scale Integration LayoutArea OptimizationAutomated Layout SynthesisFolding PatternsLayout GenerationVlsi Implementation
A PLA structure incorporating segmenting and folding features intended for use as a macro-cell for VLSI applications is described. A brief outline of a computer-aided-design system for the layout synthesis of such PLAs is given. The objectives are the attainment of compact area, low design time, and ease of design Symbolic layout generation for the PLA is treated in detail and practical design algorithms for partitioning and folding are discussed. An example is used to illustrate currently achievable results.
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An Introduction to Array Logic
H. Fleisher, L. I. Maissel · IBM Journal of Research and Development · 1975 · 188 citations
D.L. Greer · IEEE Journal of Solid-State Circuits · 1976 · 27 citations
Programmed Logic Array Optimization
Eva Roth · IEEE Transactions on Computers · 1978 · 10 citations