A 204.8GHz Static Divide-by-8 Frequency Divider in 250nm InP HBT

Abstract

We present a static divide-by-8 frequency divider with a record maximum clock frequency of 204.8GHz, designed and fabricated using 250nm InP HBTs (400GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">τ</sub> , 650GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) with a 4-metal layer, inverted thin-film microstrip wiring environment. The divider is fully static down to 4.0GHz operation. The total power dissipation is 1.82W, of which 592mW is consumed by the input-stage divider. The divider latches are formed using emitter-coupled-logic (ECL), and inductive peaking is used in series with the load resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> to minimize gate delays for highest possible divider clock rates. The circuit contains 108 HBTs and its size is 0.68 x 0.45-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .