Concepedia

Abstract

Static frequency dividers are widely used technology performance benchmark circuits. Using a 0.25 μm 530 GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /600 GHz+ f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> InP DHBT process, a static frequency divider circuit has been designed, fabricated, and measured to operate up to 200.6 GHz. The divide-by-two core flip-flop dissipates 228 mW. Techniques used for the divider design optimization and for selecting variants to maximize performance across process changes are also discussed.

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