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Parallel multi-confined (PMC) cell technology for high density MLC PRAM
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2006
Year
EngineeringEmerging Memory TechnologyComputer ArchitecturePmc Cell StructureInterconnect (Integrated Circuits)Multi-channel Memory ArchitectureAdvanced Packaging (Semiconductors)Memory DeviceElectronic PackagingParallel ComputingMicrofluidicsElectrical EngineeringComputer EngineeringCell TechnologyPmc CellMicroelectronicsMemory ArchitectureFlexible ElectronicsMicrofabricationBioelectronicsSemiconductor MemoryCvd Pcm Process
We first present a parallel multi-confined (PMC) cell structure on single contact was successfully integrated by using CVD PCM process. PMC cell shows the discrete four resistance levels with increasing applied current, and its middle resistances (D01, D10) have the low drift coefficient under 0.007. The four resistance levels were maintained up to 2E5 cycles. From simulation results, PMC cell structure is applicable to MLC PRAM device below 25nm design rule.