A systematic DFT procedure for library cells

Abstract

We present an automated procedure for improving the testability of a product by improving the testability of cells in the cell library. This method was applied to a scan flip-flop from Cyrix's standard cell library. Based on this analysis, some design and layout changes were suggested, which brought down the probability of difficult-to-detect faults by 70%, without compromising the performance or increasing the area of the circuit.