2002 · 12 citations · 15 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingFault-tolerant SystemsFault DetectionHardware Fault ToleranceReliable System DesignSequential Logic DescriptionFault Tolerance In Digital Circuits
We present a procedure to reduce sequential circuits by removing undetectable faults based on unreachable states. Procedures for obtaining unreachable stares and for identifying undetectable faults which can be the target of fault removal are presented. Experimental results for ISCAS benchmark circuits are shown.
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Graph-Based Algorithms for Boolean Function Manipulation
Bryant · IEEE Transactions on Computers · 1986 · 8.9K citations · Full text
Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
H. Cho, Gary D. Hachtel, Fabio Somenzi · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 128 citations