H. Cho

Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration

H. Cho, Gary D. Hachtel, Fabio Somenzi · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1993 · 125 citations

Engineering, Hardware Verification Language, Verification +21

ATPG aspects of FSM verification

H. Cho, Gary D. Hachtel, Seh-Woong Jeong et al. · 2002 · 122 citations

Circuit Complexity, Computational Complexity Theory, Engineering +22

Timing analysis of combinational circuits using ADDs

R. Iris Bahar, H. Cho, Gary D. Hachtel et al. · 2002 · 38 citations

Engineering, Combinational Circuits, Computer Architecture +16

Redundancy identification and removal based on implicit state enumeration

H. Cho, Gary D. Hachtel, Fabio Somenzi · 2002 · 27 citations

Circuit Complexity, Engineering, Redundancy Identification +21

New ATPG techniques for logic optimization

R. Jacoby, P. Moceyunas, H. Cho et al. · 2003 · 24 citations

Engineering, Redundancy Identification, Computer-aided Verification +16