An SOI-based three-dimensional integrated circuit technology

Abstract

Three-dimensional integrated circuits (3D-ICs) composed of active circuit layers that are vertically stacked and interconnected are expected to lead to improved logic devices, memories, CPUs, and photosensors (Akasaka, 1986). These circuits require high-density vertical interconnections (3D vias) comparable in aspect ratio to present multilevel vias (Reber and Tielert, 1996). We have constructed and tested 3D ring oscillators and fully parallel 64/spl times/64 active pixel sensors using a 3D assembly technology which utilizes SOI wafers to achieve stacking of multiple circuit layers and unrestricted placement of dense 3D vias.